With increasing processing speed of digital signals in modern circuits, the effect of noise on these signals becomes increasingly problematic. These noise problems are further exacerbated when a number of digital circuits connect to a single bus and receive the same signal.
Many techniques have been employed to reduce noise sensitivity of such circuits. In signals where the information content is coincident with the edge of the waveform (e.g., where the edge of a strobe signal is used to latch data and/or clock state machines), a “glitch” can nonetheless cause a significant problem. A glitch is a short pulse or noise spike to which circuit response is not desired. A two-dimensional de-glitch filter may, for example, be used for these types of signals, such as described in U.S. patent application Ser. No. 10/653,341, filed on Sep. 2, 2003, now U.S. Pat. No. 6,778,111, issued Aug. 17, 2004, and incorporated herein by reference.
In signals where information content is determined by signal level and a data clock, a receiver circuit may use a differential receiver to compare an input signal to a threshold level to determine if the input signal is high or low. The receiver circuit utilizes two threshold levels, a high voltage threshold and a low voltage threshold, respectively representing high and low switching levels. When the input signal rises above the high voltage threshold, the differential receiver changes state of the receiver circuit; when the input signal drops below the low voltage threshold, the differential receiver again changes the state of the receiver circuit.
The voltage difference between the low voltage threshold and the high voltage threshold is known as input hysteresis. The receiver circuit is thus often called a hysteresis receiver. The hysteresis receiver resists noise when the noise is lower in magnitude than the amount of input hysteresis, which must be less than the minimum difference between the low and high levels of the input signal to ensure correct operation.
Typically, in a bus system with multiple receiver circuits (e.g., multiple chips connected to a bus), the minimum difference between the low and high levels of the input signal, when data is valid, is reduced, thereby reducing the amount of usable input hysteresis. Often, therefore, the noise level increases above the hysteresis level; noise then transfers through the hysteresis receiver circuits. The use of ‘deep’ hysteresis levels, where the amount of input hysteresis is large, also reduces the response time of the hysteresis receiver circuit since the input signal takes longer to reach the transition threshold levels. Where the deep hysteresis levels are close to the maximum input signal levels, any reduction in input signal level (e.g., caused by temperature or bus loading variations) may cause the hysteresis receiver circuit to fail in the detection of valid transitions in the input signal. In such circumstances, information may be lost.
Another technique for reducing sensitivity to noise in digital signals is to design the receiver circuit to respond only to input pulses that exceed a predetermined minimum pulse width, thereby ignoring pulses of lesser duration. This technique is utilized within a “timing-based” receiver circuit. Typically, the timing-based receiver circuit has a timer that starts when a first transition in the input signal is detected. If a second transition occurs before the timer expires, both the first and second transitions are ignored, removing the noise. If the timer expires before the second transition occurs, the timing-based receiver circuit outputs the transition, thereby passing signal pulses to a receiving circuit. Any transition must be present at the input longer than the periodicity of the timer in order for the transition to be passed to the output of the timing-based receiver circuit.
For correct operation, the predetermined minimum pulse width in a timing-based circuit must be greater than the width of any encountered noise and also less than the pulse width of any valid signal. This timing-based receiver circuit technique is typically used in non-timing critical circuits where, for example, a slow copy of a strobe signal may be used to clock a non-timing critical state machine. A similar timing-based receiver technique reduces sensitivity of digital signals to noise by passing a first edge of the digital signal and suppressing subsequent edges for a time period set by a delay line duration. However, as the data rate of the input signal increases, the noise duration often matches or exceeds the duration of the delay in the timing-based receiver, in which case the noise is not removed.
Hysteresis and timing-based techniques may be combined in a receiver circuit. When combined, the hysteresis and timing-based receiver circuit may operate to remove certain types of noise. For example, U.S. Pat. No. 5,341,033 (the '033 patent) describes one circuit that removes noise using a hysteresis buffer with two levels of hysteresis and a timer. When the hysteresis buffer detects a transition, the timer is triggered. The timer is in feedback with the hysteresis buffer to increase the buffer's hysteresis, thereby ignoring noise until the timer expires. The circuit of the '033 patent is a first-edge pass (timing-based) noise protection circuit with hysteresis and is more suited to input signals with short duration noise (i.e., noise close to the active edge of the input signal). The '033 patent is incorporated herein by reference.
As bus speeds increase, signal periodicity decreases and noise duration becomes longer, relative to the signal period, making timing-based receivers less suitable for removing noise from the high speed bus signals. Further, Very Large Scale Integration (VLSI) implementation of a delay line incurs large variations in the operational delay period due to manufacturing tolerances and operating temperature variation. The operational delay period typically varies by a factor of two or more, causing the timing-based receiver to have unpredictable operation.